The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits), and the like requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. In fact, many modern integrated circuit chips may have one or more “logic regions” where primarily logic circuits or logic devices are made, one or more “memory regions or arrays” that primarily contain memory devices, and one or more “high-voltage” MOSFETs to improve device performance. Although the logic devices, memory devices, and high-voltage MOSFETs are often formed on the same chip and frequently share common materials, such devices do have fundamental structural differences, and they are often formed at different times during a particular process flow that is performed to form the completed integrated circuit device.
The basic structures of the logic devices, memory devices, and high-voltage MOSFETs are fabricated by forming various layers of material and thereafter patterning those layers of material using known photolithography and etching processes. Often, the basic layer “stack” for the memory devices is formed prior to fabricating the gate electrodes for the logic regions and high-voltage MOSFET regions of the device. In contrast, due to some structural similarities, the logic regions and high-voltage MOSFET regions may be fabricated, at least in part, concurrently. Thus, the process designer is often faced with the challenge of ensuring that process steps employed in the fabrication of one device do not harm other devices that are previously or concurrently fabricated.
Over recent years, there has been a constant drive to reduce the physical size of various consumer electronic products that employ integrated circuits. The demand for smaller consumer products with greater capability has resulted in the scaling or reduction in the physical size of integrated circuit devices that are employed in such consumer products. The reduction in size of the integrated circuits has been achieved by, among other things, reducing the physical size of the various semiconductor devices, e.g., the transistors, and by greatly increasing the density of such transistors on a given area of a semiconducting substrate or chip.
With reduction in physical size, however, there is a greater likelihood that the processes employed in the fabrication of one device of the integrated circuit may adversely affect the prior or concurrent fabrication of other devices due to increased proximity of the devices. In one example, it is known that the fabrication of high-voltage MOSFETs requires a “lightly-doped drain” (LDD) ion implantation step prior to the fabrication of the gate structure to ensure proper electron flow in the channel below the gate. In order to prevent ion implantation directly into the channel region during the process, a polysilicon “masking” layer is often employed over the channel region. Due to scale limitations, however, in integrated circuit designs where a logic device is disposed adjacent to the high-voltage MOSFET device, the thickness of the polysilicon layer is limited. In particular, in small scale devices, the thickness of the polysilicon masking layer may be limited such that the thickness is insufficient to adequately block ion implantation into the channel region of the high-voltage MOSFET. The presence of dopant ions in the channel may, in turn, result in degraded device performance.
Accordingly, it is desirable to provide improved methods for fabricating high-voltage MOSFETs. Additionally, it is desirable to provide methods for fabricating high-voltage MOSFETs on an integrated circuit that further includes one or more memory arrays or logic devices in close proximity thereto that do not suffer degraded performance as a result of concurrent device fabrication process limitations. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.